The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for timing driven routing for noise reduction in an integrated circuit design.
Modern day electronics include components that use integrated circuits (ICs). Integrated circuits are electronic circuits formed using Silicon as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, and resistors. Commonly known as a “chip,” an integrated circuit is generally encased in hard plastic. The components in modern day electronics generally appear to be rectangular black plastic pellets with connector pins protruding from the plastic encasement.
Circuit designers use a variety of software tools to design electronic circuits that accomplish an intended task. For example, a digital circuit may be designed to accept digital inputs, perform some computation, and produce a digital output. An analog circuit may be designed to accept analog signals, manipulate the analog signals, such as by amplifying, filtering, or mixing the signals, and produce an analog or digital output. Generally, any type of circuit can be designed as an IC.
Logical synthesis, physical synthesis, and generation of a routed and timing closed design are some of the functions of an IC design software tool. Logical synthesis is the process of designing the logical operation that is to be achieved by a circuit. Physical synthesis is the mapping, translating, or integration of that logical synthesis to the physical design components, such as logic gate and buffer circuits. Routing and timing closed design is the design produced by adjusting the wire routings and component placements in a design so that the design meets certain design criteria, such as delay or slew of signals, or wirelength restrictions.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout at very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometer across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including millions of such components interconnected to form an intended electronic circuitry. An interconnected group of components is called a “net.”
The software tools manipulate these components at the component level or at the block level. A block of components is also known as a global cell, or g-cell. A g-cell in an IC design is a portion of the IC design. One way of identifying g-cells in an IC design is to overlay a grid of imaginary vertical and horizontal lines on the design, and deeming each portion of the IC design bound by horizontal and vertical lines as a g-cell. The horizontal or vertical lines bounding a g-cell are called cut-lines.
Imposing such a grid on an IC design abstracts the global routing problem away from the actual wire implementation and gives a more mathematical representation of the task. A net may span one or more g-cells and may cross several cut lines.
An IC design software tool can, among other functions, manipulate cells or interconnect components of one cell with components of other cells to form nets. These cells are different from g-cells in that these cells are the actual logic components, such as the semiconductor gates. Interconnects between components are called wires. A wire is a connection between parts of electronic components and is formed using a metallic material that conducts electricity.
A placement problem is a problem of placing the cells of a chip such that the design meets all the design parameters of the chip. Routing is the process of connecting the pins after placement. In other words, placement results in a rendering of the components of various cells as being located in certain positions in the design, whereas routing results in a rendering of how the metal layers would be populated with that placement. A wire can be designed to take any one of several available paths in a design. Placement of a wire on a certain path, or track, is a part of routing.
A layer is typically designated to accommodate wires of a certain width (wire code). Generally, the wider the wire width of a layer or higher the height of a layer, the faster the signal propagation speed for the net routed on that layer. Faster layers, i.e., layers with larger wire widths and wire height, can accommodate fewer components or nets as compared to slower layers with narrower wire widths.
A router is a component of an IC design tool that performs the routing function. Once the placement component, known as a placer, has performed the placement function, the router attempts to connect the wires without causing congestion. For example, if a design parameter calls for no more than five wires in a given area, the router attempts to honor that restriction in configuring the wiring. Such limitations on the wiring are a type of design constraints and are called congestion constraints. Other types of design constraints may include, for example, blocked areas—cell areas where wires may not be routed.
A global router divides the routing region into g-cells and attempts to route nets through the g-cells such that no g-cell overflows its capacity. Global routing is the process of connecting a g-cell to other g-cells.
After global routing, wires must be assigned to actual tracks within each tile, followed by detail routing, which must connect each global route to the actual pin shape on the cell. Another type of router, known as the detailed router, performs the detailed routing. The global and detailed routing produced during the design process are collectively referred to as “routing” and are usually further modified during optimization of the design.